| PART |
Description |
Maker |
| IDT72V2111L20PFI IDT72V2111 IDT72V2101 IDT72V21011 |
256K x 9 SuperSync FIFO, 3.3V
512K x 9 SuperSync FIFO, 3.3V
3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO?
|
IDT[Integrated Device Technology]
|
| IDT72V2103L7-5BC IDT72V2103L7-5BCI IDT72V2103L7-5P |
128K x 18 / 256K x 9 SuperSync II FIFO, 3.3V
256K x 18 / 512K x 9 SuperSync II FIFO, 3.3V
|
IDT
|
| CY7C1380C-200AC CY7C1380C-200BGC CY7C1380C-167AC C |
Memory : Sync SRAMs
PUSHBUTTON, METAL, FLAT, 22MM 5A; Switch function type:NC/NO Mom; Voltage, contact AC max:250V; Temp, op. max:55(degree C); Temp, op. min:-20(degree C); Diameter, panel cut-out:22.2mm; Length / Height, external:32mm; Dielectric RoHS Compliant: Yes
18-Mb (512K x 36/1M x 18) Pipelined SRAM 1M X 18 CACHE SRAM, 2.8 ns, PBGA165
18-Mb (512K x 36/1M x 18) Pipelined SRAM 1M X 18 CACHE SRAM, 2.6 ns, PBGA165
18-Mb (512K x 36/1M x 18) Pipelined SRAM 512K X 36 CACHE SRAM, 2.8 ns, PBGA165
18-Mb (512K x 36/1M x 18) Pipelined SRAM 512K X 36 CACHE SRAM, 3 ns, PQFP100
18-Mb (512K x 36/1M x 18) Pipelined SRAM 512K X 36 CACHE SRAM, 2.8 ns, PQFP100
18-Mb (512K x 36/1M x 18) Pipelined SRAM 512K X 36 CACHE SRAM, 3.4 ns, PQFP100
|
Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
|
| IDT72811 IDT72821 IDT72801 IDT72841 IDT72851 IDT72 |
DUAL CMOS SyncFIFO?
512 x 9 DualSync FIFO, 5.0V
8K x9 DualSync FIFO, 5.0V
1K x 9 DualSync FIFO, 5.0V
2K x 9 DualSync FIFO, 5.0V
|
Integrated Device Techn...
Integrated Device Technolog...
IDT[Integrated Device Technology]
|
| CY7C1372CV25-167AI CY7C1372CV25-167BGI CY7C1372CV2 |
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 3 ns, PQFP100
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 3 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 3 ns, PBGA119
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 2.8 ns, PBGA119
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 2.8 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 512K X 36 ZBT SRAM, 3 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 512K X 36 ZBT SRAM, 3 ns, PQFP100
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 512K X 36 ZBT SRAM, 3.4 ns, PQFP100
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 512K X 36 ZBT SRAM, 3.4 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 12k × 36/1M × 18流水线的SRAM架构的总线延迟
CAP,Ceramic,10000pF,500VDC,10-% Tol,10% Tol,X7R-TC Code,-15,15%-TC,30ppm-TC RoHS Compliant: Yes
512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
|
Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
|
| CY7C420-25PC CY7C420-40PC CY7C420-65PC CY7C421 CY7 |
256/512/1K/2K/4K x 9 Asynchronous FIFO 2K X 9 OTHER FIFO, 40 ns, PDIP28
256/512/1K/2K/4K x 9 Asynchronous FIFO 4K X 9 OTHER FIFO, 40 ns, PQCC32
256/512/1K/2K/4K x 9 Asynchronous FIFO 256 X 9 OTHER FIFO, 40 ns, PQFP32
256/512/1K/2K/4K x 9 Asynchronous FIFO 2K X 9 OTHER FIFO, 40 ns, PQFP32
256/512/1K/2K/4K x 9 Asynchronous FIFO 2K X 9 OTHER FIFO, 20 ns, CDIP28
|
Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
|
| IDT72T54262 |
2.5V QUAD/DUAL TeraSyncDDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS 2.5V的四/双TeraSync⑩复特别提款权先进先出10的四双FIFO或x10/x20先进先出配置
|
Integrated Device Technology, Inc.
|
| 7280L20PA |
FIFO 256X9 20NS TSSOP56 512 X 9 BI-DIRECTIONAL FIFO, 20 ns, PDSO56
|
Integrated Device Technology, Inc.
|
| CY7C401-25DC CY7C401-25PC CY7C401-5PC |
64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO 64 X 4 OTHER FIFO, 34 ns, CDIP16
64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO 64 X 4 OTHER FIFO, 34 ns, PDIP16
64 x 4 Cascadable FIFO / 64 x 5 Cascadable FIFO 64 X 4 OTHER FIFO, 80 ns, PDIP16
|
Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
|
| CY7C1461AV33-100AXC CY7C1463AV33-100AXC CY7C1461AV |
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL垄芒 Architecture
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL Architecture(带NoBL结构6-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM) 36兆位米x 36 / 2 M中的x 18/512K × 72）流体系结构，通过与总线延迟（带总线延迟结构的的36 - Mbit通过的SRAM100万x 36 / 2 M中的x 18/512K × 72）流的SRAM
|
Cypress Semiconductor Corp.
|
| 7201LA20SOB 7202LA20SOB 7200L25TPI |
512 X 9 OTHER FIFO, 20 ns, PDSO28 SOIC-28
1K X 9 OTHER FIFO, 20 ns, PDSO28 SOIC-28
256 X 9 OTHER FIFO, 25 ns, PDIP28
|
Integrated Device Technology, Inc.
INTEGRATED DEVICE TECHNOLOGY INC
|
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